Many present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions, defining a transistor channel, between which a current may flow. A control voltage applied to the gate electrode controls the flow of current through the channel between the source and drain electrodes. Complementary MOS (CMOS) devices include a plurality of N-channel MOS (NMOS) transistors and a plurality of P-channel (PMOS) transistors. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors, are formed on a substrate including a crystalline semiconductor layer.
In contrast to traditional planar MOS transistors, which are fabricated using conventional lithographic fabrication methods, nonplanar MOSFETs incorporate various vertical transistor structures. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are often on the order of tens of nanometers in width. In the rapidly-advancing semiconductor manufacturing industry, CMOS FinFET devices are increasingly used in many logic and other applications and are integrated into various different types of semiconductor devices. FinFET devices often include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed. A gate is formed over and along the sides of a portion of the semiconductor fins. The use of fins increases surface areas of the channel and source/drain regions for the same area. The increased surface area in a FinFET results in faster, more reliable, and better-controlled semiconductor transistor devices that consume less power than planar devices configured to perform the same function.
For example, in low-power devices, the advantages of the FinFET architecture become more significant as the operating voltage is reduced. At 1V, the FinFET is 18% faster than the equivalent planar device, but at 0.7V, the advantage is 37%. This is because the FinFET's sub-threshold swing (the amount that the threshold voltage has to be changed to halve its leakage) is lower than in a planar device, so the device can be operated at lower threshold voltages for the same leakage. This, in turn, means that the difference between the gate and threshold voltage at very low operating voltages is much greater, exaggerating the performance advantage of very low-voltage FinFETs.
As manufacturing process progresses into smaller and smaller technology nodes, devices originally designed in a larger technology node may benefit from manufacturing in a smaller technology node in ways such as increased performance, efficiency, and decreased die size. Similarly, devices designed using planar transistors may also benefit from manufacturing using FinFETs. However, because different design rules apply to planar structure layouts and FinFET structure layouts, converting portions of the device from a planar layout to a FinFET layout by hand may be akin to creating a new design from scratch and is a highly resource intensive (in both computation and human capital) process. For product already being manufactured using planar transistors, a conversion that includes changes to semiconductor layers above the transistor level would require many new photomasks to be created, which dramatically increases the cost required to fabricate the integrated circuit.
While some methods are currently known in the art for the conversion of planar designs to FinFET designs, these methods suffer from several drawbacks. For instance, may conversion methods currently known are implemented at the reticle level, i.e., at the overall top level of the integrated circuit design. At the reticle level, verification of the functionality of the FinFET conversion is very difficult, due both to the fact that verification occurs late in the design flow, and the fact that verification at the reticle level requires data for the entire reticle, which takes a significant amount of computational time to process.
Accordingly, it is desirable to provide improved methods for converting planar integrated circuit designs to FinFET integrated circuit designs. Additionally, it is desirable to provide such methods that reduce the computational resources required to convert planar designs to FinFET designs. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of this disclosure.